Manufacturing Method of 4-Layer 2nd-Order Chip-Embedded HDI Board

Manufacturing Method of 4-Layer 2nd-Order Chip-Embedded HDI Board

Abstract

With the rapid development of printed circuit board (PCB) technology, various PCBs with embedded components have been widely used. This paper introduces a manufacturing method for a 4-layer 2nd-order chip-embedded high density interconnector (HDI) printed circuit board, including the solutions to the warpage of the asymmetric structure board and the flatness problem of the embedded chip. It shares the manufacturing experience of chip-embedded special PCBs, aiming to provide technical reference for the R&D and production of such special boards.

0 Introduction

Special printed circuit boards (PCBs) with embedded capacitors, resistors, buried or embedded metal blocks, etc., have expanded the functions and application scope of PCBs and possess high added value. However, the manufacturing difficulty of special PCBs is relatively high, and their production process differs significantly from that of ordinary PCBs. This paper develops a manufacturing method for a 4-layer 2nd-order chip-embedded high density interconnector (HDI) special PCB.

1 Analysis of Manufacturing Difficulties of 4-Layer 2nd-Order Chip-Embedded HDI Board

1.1 Laminated Board Structure

The structure of the 4-layer 2nd-order chip-embedded HDI board is shown in Figure 1.

1.2 Analysis of Manufacturing Difficulties

(1) As can be seen from Figure 1, this PCB adopts an asymmetric structure with two times of single-sided blind vias. The manufacturing process requires two laminations: the first lamination embeds the chip into the core boards L3~L4 and laminates it with L2, completing the lamination of L2~L4; then the blind vias of L2~L3 and the circuits of L2 are fabricated, followed by the second lamination to bond L1~L2. Due to the asymmetric laminated structure, the PCB is prone to excessive warpage after manufacturing. How to optimize the lamination structure to ensure good bending resistance of the PCB is one of the key control points of this PCB (the board warpage is required to be within 0.65~1.52 mm).

(2) The designed dielectric layer thickness of the laser blind vias of this PCB is 0.172 mm, and the blind via diameter is 0.2 mm, which are significantly larger than those of ordinary HDI (dielectric layer thickness 0.075 mm, blind via diameter 0.1 mm). Therefore, a high-energy laser drilling machine should be selected for laser drilling of blind vias. In addition, a special electroplating filling process needs to be developed for the blind via electroplating filling process.

(3) The chip is exposed on the L4 side and needs to undergo chemical immersion processes such as copper deposition, electroplating, and horizontal line treatment during manufacturing. If the resin filling between the chip and the substrate is insufficient during lamination, resulting in gaps or voids, the chemical solution will penetrate into the gaps and cause chip corrosion. How to avoid residual voids or bubbles during lamination is a key issue in the lamination process. For this structure, special attention must be paid to controlling the resin flow during lamination and the resin filling effect between the chip and the substrate after lamination, ensuring 100% no voids.

(4) Structurally, one side of the chip is bonded to the 1080 prepreg (PP) of L2~L3 layers. Therefore, the surface treatment of the chip before the first lamination is crucial to improving the bonding force. The chip needs to undergo brown oxidation surface treatment before lamination to increase surface roughness. Due to the small size of the chip, the fan in the brown oxidation drying section should be turned off to prevent the chip from being blown away by hot air. After brown oxidation, the chip should be statically baked in an oven to remove moisture at 120 ℃ for 1 h.

(5) The packaging material of this chip is ceramic with a low coefficient of thermal expansion (CTE). Since the chip is embedded inside the PCB, the CTE of the PCB material needs to be close to that of the chip to meet the matching requirement. Therefore, how to select the PCB material is one of the key design points of this board.

1.3 Selection of PCB Structural Materials

Based on the analysis of manufacturing difficulties, the selection of materials for this board should consider aspects such as board warpage improvement, resin filling, and CTE.

Research on the improvement of warpage of asymmetric structure boards shows that the thinner the glass fiber cloth used in making PP, the more favorable it is for improving the warpage of asymmetric structure boards. When selecting materials for this board, both the laminated PP and core boards are required to use thin glass fiber PP. The 0.2 mm core board is required to be laminated with 313×3 PP, and the lamination uses 1080 PP (high resin content, 68%). In addition, selecting materials with low CTE and high Tg (glass transition temperature) has better dimensional stability (selecting boards with Tg ≥ 190 ℃).

2 Targeted Process Flow

2.1 Core Board Fabrication

As shown in Figure 1, there are 1, 2, 3, and 4 core boards. Only the L3 layer circuit is fabricated on core board 1, with no copper on the other side, and target holes are punched after etching; core board 2 and core board 3 have no circuits, and target holes are punched; the L4 layer of core board 4 is fully coppered, and the other side is a bare board, and target holes are punched after etching.

2.2 Core Board Slot Milling and PP Slot Milling

A CNC milling machine with slot milling accuracy within ±0.050 mm is selected for slot milling, and a slot 0.075 mm larger than the single side of the chip is milled; the same method is used to mill a slot 0.125 mm larger than the single side of the chip on the PP. The CNC milling machine is preferably installed in a lamination cleanroom, because PP needs to be stored in an environment with stable temperature and humidity and qualified cleanliness to ensure good lamination quality.

2.3 First Lamination

After the first lamination, the thickness of the PCB board ranges from 1.35 to 1.65 mm.

(1) The core boards (1, 2, 3, 4) are normally subjected to brown oxidation; the chip needs to undergo brown oxidation with a carrier. Special attention should be paid to turning off the air blowing when the chip passes through the drying section. After brown oxidation, the chip is baked in an oven at 120 ℃ for 1 h.

(2) To avoid chip deviation caused by core board sliding during lamination, the alignment deviation of the core board is required to be within 0.075 mm, and the positioning method adopts pin lamination (PIN LAM); if there is no PIN LAM lamination equipment, 12 rivets should be used to fix the core board, and the rivets are fused with an electromagnetic hot-melt furnace after completion.

(3) During lamination, a resin blocking film should be first laid on the steel plate: if it is a PIN LAM press, the resin blocking film needs to be punched first, and the PP also needs to be punched first; if it is rivet and fusion positioning, the core board with completed riveting and fusion is placed on the resin blocking film. Wear rubber gloves to put the chip into the slot, stack the 1080×2 PP between L2~L3, cover the L2 layer copper foil, and finally cover the steel plate, totaling 10 layers.

(4) The setting of lamination parameters is crucial. After high-temperature curing of lamination, the pressure in the cooling section is set at 10 kg/cm² or below to allow the PCB to cool slowly under low pressure; another key point is to ensure sufficient resin filling in the gaps around the chip, so 1080 PP with 68% resin content is selected. During lamination, when the material temperature is in the range of 80~120 ℃, the heating rate should be increased (3.5 ℃/min; the higher the heating rate, the better the resin fluidity and filling property), and a higher pressure at the pressure transfer point (32 kg/cm²) should be set.

2.4 Post-Processing After First Lamination

After the first lamination, the specific processing steps are as follows:

(1) Grind the board edge and drill positioning holes: use an X-ray drilling machine to drill the positioning holes of the PCB, and process the board edge with a cutting and grinding line.

(2) Treat the residual resin on the chip surface: use laser to treat the residual resin on the chip surface to ensure the proportion reaches 90%.

(3) Remove the board surface resin slag: send it to the copper deposition process for desmearing to remove the residual resin on the PCB copper surface.

(4) Check the chip flatness: use a 3D measuring instrument for detection, requiring the flatness between the chip and the board surface to be -10~+20 μm.

2.5 L2 Laser Drilling of Blind Vias

The specific steps for L2 laser drilling of blind vias are as follows:

(1) Drill positioning holes, expose with a special photoresist dry film, pass through acid etching to etch out the blind via window positions.

(2) Perform laser drilling of blind vias on the L2 surface with a hole diameter of 0.2 mm, using a Mitsubishi laser drilling machine.

2.6 L2 Blind Via Metallization

The specific steps for L2 blind via metallization are as follows:

(1) Perform plasma desmearing after laser drilling to remove residual resin in the blind vias.

(2) Pass through a cleaning machine (turn off the brushing section) for chemical cleaning of blind vias, and note that the water washing pressure is set at the upper limit.

(3) Use a special automated optical inspection (AOI) machine to inspect the bottom of the L2 blind vias to confirm no resin residue in the holes.

(4) Bake the board at 200 ℃ for 2 h before chemical copper deposition, and then complete the chemical copper deposition on the horizontal copper deposition line.

2.7 L2 Via Filling Electroplating

The specific steps for L2 via filling electroplating are as follows:

(1) During the first blind via electroplating filling, no current is applied to the non-blind via surface. The minimum hole copper thickness of the blind via is 15 μm, and the board surface copper thickness is 75~95 μm.

(2) Fabricate the via plating dry film, complete the fabrication in the outer layer circuit process, retain the blind vias, and cover the entire non-blind via surface with the film.

(3) Perform the second via filling electroplating, only plating the holes without plating the board surface, ensuring 100% filling of the blind vias.

(4) Perform stripping treatment to remove the dry film on the board surface on the stripping line.

(5) During the board grinding treatment, only turn on the brushing of the L2 surface, not the L4 surface. After grinding, the board surface copper thickness is controlled at 65~85 μm, the copper filling depression ≤ 20 μm, and the protrusion ≤ 25 μm.

(6) Perform board surface electroplating after grinding. The minimum board surface copper thickness of L2 is controlled at 105 μm, and no current is applied to the L4 surface.

2.8 L2 Layer Circuit Fabrication

The specific steps for L2 layer circuit fabrication are as follows:

(1) Use photoresist dry film and laser direct imaging (LDI) for pattern transfer on the L2 layer, apply corrosion-resistant dry film on the L4 layer, and perform full exposure treatment.

(2) Etch the board on the acid etching line, etch out the L2 layer circuit, resist corrosion on the L4 layer, and perform stripping treatment after etching.

(3) Inspect the L2 layer circuit on the AOI machine.

2.9 Second Lamination

The specific steps for the second lamination are as follows:

(1) Bake the board at 120 ℃ for 2 h before brown oxidation, and bake again at 120 ℃ for 2 h after brown oxidation.

(2) Pre-laminate the board, and place 1080×2 PP between L1~L2 layers.

(3) Before lamination, first place the copper foil upside down on the steel plate (the rough surface of the copper foil is in contact with the steel plate); or a release film, then place the pre-laminated board with the L4 surface facing down, and place 17 μm copper foil on the 1080×2 PP of L1~L2.

(4) Control the lamination parameters. The lamination intensity in the cooling section is set below 10 kg/cm² to allow the PCB to cool slowly under low pressure and reduce the internal stress generated by lamination.

2.10 Post-Processing After Second Lamination

After the second lamination, the specific processing steps are as follows:

(1) After lamination, first use an X-ray drilling machine to drill positioning holes, then perform filleting and edge grinding on the cutting and grinding line.

(2) Send the PCB to the copper deposition process for desmearing to remove residual resin on the board surface.

2.11 L1 Copper Reduction

The processing steps for L1 copper reduction are as follows:

(1) Fabricate the outer layer dry film, do not cover the L1 layer, and cover the L4 layer with the film.

(2) Reduce the copper thickness of the L1 layer to 7~9 μm on the copper reduction line.

(3) Perform stripping treatment to remove all the dry film covering the L4 layer.

2.12 L1 Laser Drilling

The processing steps for L1 laser drilling are as follows:

(1) Expose the blind via positions on the L1 surface with photoresist dry film for window opening, fully expose the L4 surface to make a corrosion-resistant dry film; pass through acid etching to etch out the blind via positioning window on the L1 surface; perform stripping treatment.

(2) Laser drilling of blind vias: drill holes from the L1 surface with a hole diameter of 0.2 mm, using a Mitsubishi laser drilling machine.

2.13 L1 Blind Via Metallization

The processing steps for L1 blind via metallization are as follows:

(1) Perform plasma desmearing after laser drilling.

(2) Pass through a cleaning machine for chemical cleaning of blind vias, and turn off the brushing section before cleaning.

(3) Use a special AOI inspection machine to inspect the L1 blind vias, focusing on checking for resin residue at the bottom of the blind vias.

(4) Bake the board at 200 ℃ for 2 h before chemical copper deposition, then process the board on the horizontal copper deposition line.

2.14 L1 Via Filling Electroplating

The processing steps for L1 via filling electroplating are as follows:

(1) During the first electroplating filling, the minimum hole copper thickness of the blind via is 15 μm, the board surface copper thickness is 50~70 μm; no current is applied to the L4 surface.

(2) After the first via filling electroplating, fabricate the via plating dry film on the L1 surface, retain the blind via positions, and fully cover the L4 surface with the dry film.

(3) Perform the second via filling electroplating, only plating the holes; no current is applied to the L4 surface.

(4) Remove the dry film on the board surface on the stripping line.

(5) During the board grinding treatment, only turn on the brushing of the L1 surface, not the L4 surface. After grinding, the board surface copper thickness is controlled at 40~60 μm, the copper filling depression ≤ 20 μm, and the protrusion ≤ 25 μm.

2.15 Through-Hole Fabrication

The processing steps for through-hole fabrication are as follows:

(1) Send to the mechanical drilling process for through-hole fabrication.

(2) Perform chemical copper deposition: bake the board at 200 ℃ for 2 h before copper deposition, then complete the copper deposition process normally.

(3) Board surface electroplating: perform board surface electroplating after grinding, electroplate the L1 layer, and no current is applied to the L4 layer.

2.16 Outer Layer Circuit Fabrication

The processing steps for outer layer circuit fabrication are as follows:

(1) Produce using special circuit data, photoresist dry film, and LDI exposure machine.

(2) Etch the board on the acid etching line, retain the L1 layer circuit, and the L4 layer has no circuit.

(3) Inspect the outer layer circuit on the AOI machine.

2.17 Solder Mask and Subsequent Processes

The specific steps of solder mask and subsequent processes are as follows:

(1) Solder mask adopts the normal process: use volcanic ash grinding, screen printing, low-temperature baking, exposure, development, high-temperature baking; the chip position on the L4 layer is exposed copper, and other positions are fully covered with solder mask.

(2) The surface treatment method of this board is electroless gold plating, adopting the normal process.

(3) Complete the forming process with a CNC milling machine.

(4) During the circuit open-short circuit test, note that the voltage the chip can withstand is ≥ 1000 V.

(5) Use a special board warpage baking oven for pressing and baking at 150 ℃ for 4 h, then 100% pass the board warpage testing machine (the board warpage is required to be within 0.65 mm/1.52 mm).

(6) Finally, perform the board surface quality inspection: inspect the PCB appearance with an automated visual inspection (AVI) machine; after the quality inspection department conducts random inspection and confirms qualification, perform packaging and delivery.

3 Quality Analysis of Key Process Items

3.1 Board Warpage Data

After the board warpage pressing and baking treatment, the board warpage data of 50 PCS finished units are sampled and tested. The required board warpage is within 0.65 mm/1.52 mm, and the actual measurement is 0.53~0.63 mm/1.41~1.51 mm, which meets the requirements.

From the measured data, although the board has an asymmetric structure, by optimizing the material selection, adjusting the lamination parameters, and setting the board warpage pressing process before the final inspection, the board warpage data is 100% within the customer's acceptable standard range.

3.2 Chip Flatness Data

After lamination, the flatness range of the chip is required to be concave/convex -10~+20 μm. 50 chip positions are sampled and measured after desmearing, and the concave-convex data is -1.0~-8.0 μm. After this lamination, the chip flatness data is within the required range and all are negative.

3.3 Cross-Sectional Observation of Voids

After lamination, 20 chips are taken for cross-sectional observation to confirm whether there are voids between the chip and the substrate. No voids are found in all 20 cross-sections. It can be seen that during lamination, 1080 PP with high resin content is used, and the core board is slot-milled with a high-precision CNC milling machine, controlling the slot width within 0.075 μm on a single side, which ensures the resin filling effect.

3.4 Reflow Soldering Reliability

5 PCS of finished products are passed through the reflow soldering oven 3 times at 270 ℃, and cross-sectional analysis is performed to check for separation between the chip and the substrate. The results show that no separation between the chip and the substrate is found, and no fracture is found at the connection between the chip and the blind vias.

4 Conclusion

In-depth research is conducted on this 4-layer 2nd-order chip-embedded PCB, and corresponding control schemes are formulated according to different problem points. Through process test verification, the board warpage data, chip flatness, reflow soldering reliability evaluation data, etc., are all within the customer's acceptable standard range, verifying the quality feasibility of the manufacturing scheme. However, the manufacturing process is relatively complex, with 51 steps, which needs further optimization.

by Chen xudong