Advanced Packaging Substrates: The Cornerstone of AI Chips
Release time:
2025-11-10
Artificial Intelligence (AI) is a representative of current technological development, and its application (AI+) has become a new trend across all industries. The core technology of AI relies on AI chips, and the functionality of chips must be realized through packaging into integrated circuits (ICs). An indispensable carrier for chip packaging is the packaging substrate (base plate). It can be seen that advanced packaging technology is the foundation for AI development, and packaging substrates are the cornerstone of this foundation.
AI computing units have extremely strict requirements for bandwidth and latency, requiring extremely short and fast interconnections. Heterogeneous integration and advanced packaging technologies have become new growth drivers for realizing the vision of "Moore's Law" in integrated circuits. Currently, representative advanced packaging technologies for AI chips include chip on wafer on substrate (CoWoS), co-packaged optics (CPO), chip-on-panel-on-substrate (CoPoS), and system on wafer (SoW). These packaging technologies can achieve denser integration of computing and memory, shorten interconnection lengths, and improve heat dissipation and power characteristics, thereby enabling AI chips to meet functional requirements. AI servers and high-performance computing (HPC) data centers require hardware with high processing speeds, high communication speeds (low latency and high bandwidth), and high storage capacity. The high-speed interconnection technology of these hardware has become one of the key pillars for improving system computing capabilities. Achieving high-speed interconnections mainly relies on technological advancements in packaging substrates and PCBs, including the development of redistribution layer (RDL) and interposer technologies.
Currently, packaging substrates are developing towards higher layer counts, higher density, smaller spacing, and larger sizes. Over the past 20 years, the size of packaging substrates has increased by more than 20 times (e.g., from 30 mm×30 mm to 138 mm×138 mm), the number of layers has increased by more than 4 times (e.g., from 6 to 28 layers), line width and spacing have been reduced by 10 times (e.g., from 50 μm to 5 μm), and the comprehensive interconnection capability has increased by more than 24,000 times. Currently, packaging substrates have evolved from organic substrates to silicon substrates and glass substrates. At the same time, to ensure stability and reliability, the base materials of these substrates are developing towards lower dielectric constants, dielectric loss factors, and thermal expansion coefficients. In addition, AI application terminals have stricter requirements for PCBs, such as high frequency, high speed, high density, high reliability, and low energy consumption. These requirements are reflected in high-end IC substrates, high-level HDI boards, high-multilayer boards, etc.
The current AI wave is a great opportunity to promote the upgrading of the entire electronic circuit industry. Our journal currently has a column on HDI boards/substrates. We welcome more related contributions to exchange new technologies and enable PCBs and packaging substrates to better play their cornerstone role in AI semiconductors.
By Gongyonglin
Lihai Industrial Park, Baohuan Middle Road, Shatian Town, Dongguan , China.
Room 2314-2315, Zhonghui IFC Nansha District, Guangzhou.
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